Parallel Architecture for the VLSI Implementation
نویسنده
چکیده
Error detection and correction plays a very important role in data communication. Various codes such as convolutional and block codes are available for the purpose of error detection and correction. Among the block codes Reed-Solomon code provides several advantages. Reed-Solomon codes are powerful error-correcting codes that finds wide applications in many fields. The soft-decision decoding of Reed-Solomon codes provides reliable information from the channel into the decoding process. Many soft-decision decoding algorithms are available. Among them the Koetter-Vardy algorithm is used in this paper. The gain of soft-decision decoding algorithm is several db greater than hard-decision decoders. The algorithm consists of three parts namely a soft decision front end, an interpolation processor, and a factorization step. Among the three the interpolation step is little complicated. This paper provides a parallel architecture for the VLSI implementation of the interpolation processor.
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